The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2010

Filed:

Jan. 30, 2004
Applicants:

Philip B. James-roxby, Longmont, CO (US);

Gordon J. Brebner, Monte Sereno, CA (US);

Eric R. Keller, Boulder, CO (US);

Chidamber R. Kulkarni, San Jose, CA (US);

Inventors:

Philip B. James-Roxby, Longmont, CO (US);

Gordon J. Brebner, Monte Sereno, CA (US);

Eric R. Keller, Boulder, CO (US);

Chidamber R. Kulkarni, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of the integrated circuit is configured to have a plurality of thread circuits and an interconnection topology amongst the plurality of thread circuits. Messages are concurrently processed using the plurality of thread circuits. Operation of at least one thread circuit of the plurality of thread circuits is controlled in accordance with control data received via the interconnection topology from at least one other thread circuit of the plurality of thread circuits.


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