The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 2010
Filed:
Feb. 05, 2008
Robert H. Bell, Austin, TX (US);
Thomas W. Chen, Austin, TX (US);
Venkat R. Indukuru, Austin, TX (US);
Pattabi M. Seshadri, Austin, TX (US);
Madhavi G. Valluri, Leander, TX (US);
Robert H. Bell, Austin, TX (US);
Thomas W. Chen, Austin, TX (US);
Venkat R. Indukuru, Austin, TX (US);
Pattabi M. Seshadri, Austin, TX (US);
Madhavi G. Valluri, Leander, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A test system or simulator includes an IC test application sampling software program that executes test application software on a semiconductor die IC design model. The test application sampling software includes trace, simulation point, CPI error, clustering and other programs. IC designers utilize the test application sampling software to evaluate the performance characteristics of IC designs with test software applications. The test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software. The test application sampling software analyzes microarchitecture dependent information that it uses to generate the FBVs. Test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing an instruction budgeting method. Designers use the test system with test application sampling software to evaluate IC design models by using the representative test application software program.