The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2010

Filed:

Mar. 11, 2008
Applicants:

Chun Gi Lyuh, Daejeon, KR;

Yil Suk Yang, Daejeon, KR;

SE Wan Heo, Busan, KR;

Soon IL Yeo, Daejeon, KR;

Tae Moon Roh, Daejeon, KR;

Jong Dae Kim, Daejeon, KR;

Ki Chul Kim, Seoul, KR;

SE Hoon Yoo, Seoul, KR;

Inventors:

Chun Gi Lyuh, Daejeon, KR;

Yil Suk Yang, Daejeon, KR;

Se Wan Heo, Busan, KR;

Soon Il Yeo, Daejeon, KR;

Tae Moon Roh, Daejeon, KR;

Jong Dae Kim, Daejeon, KR;

Ki Chul Kim, Seoul, KR;

Se Hoon Yoo, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.


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