The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 2010
Filed:
Apr. 17, 2009
Seiji Otake, Kumagaya, JP;
Shuichi Kikuchi, Gunma, JP;
Yasuhiro Takeda, Ogaki, JP;
Kenichi Maki, Ibaraki, JP;
Seiji Otake, Kumagaya, JP;
Shuichi Kikuchi, Gunma, JP;
Yasuhiro Takeda, Ogaki, JP;
Kenichi Maki, Ibaraki, JP;
Sanyo Electric Co., Ltd., Osaka, JP;
Sanyo Semiconductor Co., Ltd., Gunma, JP;
Abstract
This invention provides a DMOS transistor that has a reduced ON resistance and is prevented from deterioration in strength against an electrostatic discharge. An edge portion of a source layer of the DMOS transistor is disposed so as to recede from an inner corner portion of a gate electrode. A silicide layer is structured so as not to extend out of the edge portion of the source layer. That is, although the silicide layer is formed on a surface of the source layer, the silicide layer is not formed on a surface of a portion of a body layer, which is exposed between the source layer and the inner corner portion of the gate electrode. As a result, the strength against the electrostatic discharge can be improved, because an electric current flows almost uniformly through whole of the DMOS transistor without converging.