Method for forming offset spacers for semiconductor device arrangements

Abstract

Methods are provided for the fabrication of abrupt and tunable offset spacers for improved transistor short channel control. The methods include the formation of a gate electrode within a dielectric layer, with only a top portion of the gate electrode exposed. Silicon is added on the top portion of the gate electrode, by selective epitaxial growth, for example. Etching of the dielectric layer is performed with added silicon at the top portion of the gate electrode serving as a silicon mask to prevent etching of the dielectric layer directly underneath the silicon mask, which includes overhangs over the gate electrode sidewalls. The etching creates offset spacers in a production-worthy manner, and can be used to form offset spacers that are asymmetrical in width. By running the methodology in a microloading regime, wider offset spacers may be created on narrower polysilicon gate features, thereby improving Vt roll-off.