The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 2010
Filed:
May. 24, 2007
Jonathan J. Ho, Fremont, CA (US);
Yan Wang, Campbell, CA (US);
Xin X. Wu, Fremont, CA (US);
Jane W. Sowards, Fremont, CA (US);
Jonathan J. Ho, Fremont, CA (US);
Yan Wang, Campbell, CA (US);
Xin X. Wu, Fremont, CA (US);
Jane W. Sowards, Fremont, CA (US);
XILINX, Inc., San Jose, CA (US);
Abstract
Computer-implemented methods of generating netlists for use in post-layout simulation procedures. A lookup table includes a predetermined set of features (e.g., transistors of specified sizes and shapes) supported by an integrated circuit (IC) fabrication process, with dimensions and process induced dimension variations being included for each feature. A netlist is extracted from an IC layout, the extracted netlist specifying circuit elements (e.g., transistors) implemented by the IC layout and interconnections between the circuit elements. A search pattern is run on the IC layout to identify features in the IC layout corresponding to features included in the lookup table. Circuit elements in the extracted netlist that correspond to the identified features are then modified using values from the lookup table, and the modified netlist is output. In some embodiments, the netlist extraction, search pattern, and netlist modification are all performed as a single netlist generation step.