The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7764761 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 27, 2010

Filed:

Aug. 07, 2008
Applicants:

Chih-jen Shih, Changhua County, TW;

Chun-yuan Hsu, Taipei County, TW;

Che-cheng Kuo, Taoyuan County, TW;

Chun-kuo Yu, Taoyuan County, TW;

Inventors:

Chih-Jen Shih, Changhua County, TW;

Chun-Yuan Hsu, Taipei County, TW;

Che-Cheng Kuo, Taoyuan County, TW;

Chun-Kuo Yu, Taoyuan County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A shift register apparatus and a method thereof are provided. The technique manner submitted by the present invention utilizes two NMOS transistors for pulling down the voltage level of the scan signals output by the shift registers within the shift register apparatus to the low level gate voltage, wherein one of the NMOS transistors is controlled by a control unit, and the other NMOS transistor is controlled by a clock signal or the inverted clock signal provided to the shift registers. Therefore, shifting amount of the threshold voltage of those NMOS transistors can trend to be flat, and the reliability of those NMOS transistors can be promoted. In addition, since only one control unit is needed to dispose in each shift register so that the layout area of whole shift register apparatus can be reduced, and the panel with narrow frame size also can be achieved by the present invention.


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