The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 2010
Filed:
Jul. 08, 2008
Takashi Ryu, Kyoto, JP;
Takuya Ishii, Osaka, JP;
Naoyuki Nakamura, Kyoto, JP;
Hirohisa Tanabe, Kyoto, JP;
Takashi Ryu, Kyoto, JP;
Takuya Ishii, Osaka, JP;
Naoyuki Nakamura, Kyoto, JP;
Hirohisa Tanabe, Kyoto, JP;
Panasonic Corporation, Osaka, JP;
Abstract
A reference voltage is applied from a reference voltage generating circuit to the non-inverting input terminal of an amplifier for supplying a drive voltage to the gate terminal of an NMOS transistor, and the output voltage appearing at the source terminal of the NMOS transistor is divided by a resistor pair and applied to the inverting input terminal of the amplifier. The voltage obtained by adding a voltage equal to or higher than the voltage for sufficiently driving the NMOS transistor to the output voltage appearing at the source terminal of the NMOS transistor is generated by a charge pump circuit and supplied to the amplifier as a power supply voltage. With this configuration, the drive voltage for the NMOS transistor is suppressed to the required minimum voltage while the drive voltage is obtained securely. The power consumption in the amplifier can thus be suppressed.