The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2010

Filed:

Sep. 07, 2007
Applicants:

Ming-yan Chen, Hsinchu, TW;

Yi-wei Chen, Hsinchu, TW;

Yi-sheng Cheng, Hsinchu, TW;

Ying-chi Liao, Hsinchu, TW;

Inventors:

Ming-Yan Chen, Hsinchu, TW;

Yi-Wei Chen, Hsinchu, TW;

Yi-Sheng Cheng, Hsinchu, TW;

Ying-Chi Liao, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01); H01L 21/8238 (2006.01); G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
Abstract

A pixel structure and a fabrication method thereof are provided, wherein a semiconductor pattern and a data line are defined simultaneously by performing a half-tone or grey-tone masking process. In addition, a self-alignment manner is further adopted to fabricate a lightly doped region with symmetric lengths on two sides of a channel region through steps such as photoresist ashing and etching, so as to prevent the problem of misalignment of mask generated when a mask is used to define the lightly doped region in the conventional art. Furthermore, a source pattern and a drain pattern are made to directly contact a source region and a drain region of the semiconductor pattern, such that a process of fabricating a via is omitted. Besides, in the present invention, a common line pattern surrounding the peripheral of the pixel region is also formed to improve the aperture ratio of the pixel structure.


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