The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 2010
Filed:
Sep. 04, 2008
John Jensen, Portland, OR (US);
Robert Muller, Portland, OR (US);
John Jensen, Portland, OR (US);
Robert Muller, Portland, OR (US);
LSI Corporation, Milpitas, CA (US);
Abstract
A Pseudo Low Volume Reticle (PLVR) which consists of multiple design layers on a single reticle. Specifically, the reticle can include two instances of each layer in order to facilitate die-to-die inspection techniques. A scribe is wrapped around each instance of the layer, such that both the frame and active area of the chip can be inspected with the die-to-die method. The chip consists of design data for a given part. The scribe, or frame, is preferably standard data across products which is used for yield and in line testing during the chip manufacturing process. Since only one chip and scribe unit is necessary to manufacture a device at each layer, it is only necessary that one chip and scribe instance yield during the reticle manufacturing process.