The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2010
Filed:
May. 15, 2007
Reiner Bidenbach, Vörstetten, DE;
Joerg Franke, Freiburg, DE;
Joachim Ritter, Lörrach, DE;
Christian Jung, Simonswald, DE;
Reiner Bidenbach, Vörstetten, DE;
Joerg Franke, Freiburg, DE;
Joachim Ritter, Lörrach, DE;
Christian Jung, Simonswald, DE;
Micronas GmbH, Freiburg, DE;
Abstract
The invention relates to a circuit configuration with a serial test interface (TIF) to control a test operation mode, a freely programmable digital processor (CPU), a housing (G) for the accommodation of a test interface (TIF) and the processor (CPU) with terminals or connectors (C, C) for data and/or signal exchange with external components and setups. At one of the terminals (C), a modulated supply voltage (VDD) can be received the transfer of data (d) and or a clock (T) by using at least two voltage levels (V, V) that can be controlled and which are different from a supply voltage level (V) that is designed to feed the circuitry with a supply operating voltage. Furthermore, the invention relates to a serial test operation method for such a circuit configuration.