The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2010
Filed:
Jun. 14, 2006
Taketo Heishi, Osaka, JP;
Shuichi Takayama, Hyogo, JP;
Tetsuya Tanaka, Osaka, JP;
Hajime Ogawa, Kyoto, JP;
Nobuo Higaki, Hyogo, JP;
Taketo Heishi, Osaka, JP;
Shuichi Takayama, Hyogo, JP;
Tetsuya Tanaka, Osaka, JP;
Hajime Ogawa, Kyoto, JP;
Nobuo Higaki, Hyogo, JP;
Panasonic Corporation, Osaka, JP;
Abstract
In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.