Handling of cache accesses in a data processing apparatus

Abstract

The present invention provides a data processing apparatus and method for handling cache accesses. The data processing apparatus comprises a processing unit operable to issue a series of access requests, each access request having associated therewith an address of a data value to be accessed. Further, the data processing apparatus has an n-way set associative cache memory operable to store data values for access by the processing unit, each way of the cache memory comprising a plurality of cache lines, and each cache line being operable to store a plurality of data values. The cache memory further comprises for each way a TAG storage for storing, for each cache line of that way, a corresponding TAG value. The cache memory is operable, when the processing unit is issuing access requests specifying data values held sequentially in a cache line of a current way of the cache memory, to perform a speculative lookup in at least one TAG storage to determine whether the TAG value associated with the next cache line in one way associated with the at least one TAG storage equals an expected tag value. If that TAG value does equal the expected tag value, and following an access request identifying a last data value in the cache line of the current way, a further access request is issued identifying the next cache line, then the cache memory is operable, without further reference to any TAG storage of the cache memory, to access from that next cache line of the one way the data value the subject of the further access request. This provides significant power savings when handling accesses to a cache memory.