Data processing apparatus simulation by generating anticipated timing information for bus data transfers

Abstract

Simulation of the operation of a data processing apparatus having a number of master logic units and slave logic units coupled via a bus is provided. The data processing apparatus performs data transfers between the master logic units and the slave logic units over the bus. Anticipated timing information for each successive data transfer over the bus is generated by assuming that each successive data transfer can occur with exclusive access to the bus, determining whether the anticipated timing information indicates that two or more concurrent data transfers would occur on the bus, and in the event that the anticipated timing information indicates that two or more concurrent data transfers would occur on the bus, generating revised timing information for those data transfers, the revised timing information being generated using bus status information until those data transfers have been completed.