The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2010
Filed:
Sep. 27, 2006
Applicants:
Michael J. Degerstrom, Rochester, MN (US);
Matthew L. Bibee, Bloomington, MN (US);
Inventors:
Michael J. Degerstrom, Rochester, MN (US);
Matthew L. Bibee, Bloomington, MN (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
Various port reduction methods are employed to reduce the number of port definitions in a simulation file. A ground port reduction method is first employed to reduce certain power supply reference connections to an absolute ground reference for the circuit model. Next, all commonly defined port definitions are combined into a single port definition. Finally, a current analysis is used to further reduce the number of port definitions in the simulation file by removing the current return ports from the simulation file.