The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2010
Filed:
Oct. 13, 2004
Byoung Ho Lim, Kumi-si, KR;
Soon Sung Yoo, Gunpo-si, KR;
Chang Deok Lee, Cheongju-si, KR;
Seung Hee Nam, Suwon-si, KR;
Jae Young OH, Uiwang-si, KR;
Hong Sik Kim, Seoul, KR;
Hee Young Kwack, Seoul, KR;
Byoung Ho Lim, Kumi-si, KR;
Soon Sung Yoo, Gunpo-si, KR;
Chang Deok Lee, Cheongju-si, KR;
Seung Hee Nam, Suwon-si, KR;
Jae Young Oh, Uiwang-si, KR;
Hong Sik Kim, Seoul, KR;
Hee Young Kwack, Seoul, KR;
LG Display Co., Ltd., Seoul, KR;
Abstract
A TFT array substrate is fabricated in a reduced number of processes. The TFT array substrate includes gate and data pads with enlarged contact areas to facilitate contact with an inspecting pin of an inspection device. An LCD incorporating the TFT array substrate is inspected by contacting the inspecting pin to the gate and data pads. The TFT array substrate includes first, second, and third conductive pattern groups. The first conductive pattern group includes a gate electrode, a gate line, and a lower gate pad electrode. The second conductive pattern group includes source and drain electrodes, a data line, and a lower data pad electrode. The third conductive pattern group includes a pixel electrode, and upper gate and data pad electrodes. A semiconductor pattern is along and beneath the second conductive pattern group. Gate insulating and protective film patterns are at areas not occupied by the third conductive pattern group.