The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 2010
Filed:
Mar. 03, 2009
Alireza Moini, Balmain, AU;
Kia Silverbrook, Balmain, AU;
Paul Lapstun, Balmain, AU;
Peter Charles Boyd Henderson, Balmain, AU;
Zhenya Alexander Yourlo, Balmain, AU;
Matthew John Underwood, Balmain, AU;
Nicholas Damon Ridley, Balmain, AU;
Alireza Moini, Balmain, AU;
Kia Silverbrook, Balmain, AU;
Paul Lapstun, Balmain, AU;
Peter Charles Boyd Henderson, Balmain, AU;
Zhenya Alexander Yourlo, Balmain, AU;
Matthew John Underwood, Balmain, AU;
Nicholas Damon Ridley, Balmain, AU;
Silverbrook Research Pty Ltd, Balmain, New South Wales, AU;
Abstract
A photodetecting circuit is disclosed. The photodetecting circuit includes a photodetector for generating a signal in response to incident light, a storage node having first and second node terminals, a transfer transistor, disposed intermediate the first node terminal of the storage node and the photodetector, for electrically connecting the first node terminal and the photodetector upon receiving a transfer signal to a gate of the transfer transistor, allowing charge stored in the storage node to change based on the signal of the photodetector, a reset transistor, disposed intermediate a reset voltage node and the first node terminal of the storage node, for electrically connecting the first node terminal to the reset voltage node upon receiving a reset signal to a gate of the reset transistor, and an output circuit for generating an output signal during a read period of the photodetecting circuit, the output signal being at least partially based on a voltage at the first terminal. The photodetecting circuit is configured to receive the reset signal, receive the transfer signal, and receive a compensation signal at the second terminal of the storage node at least during the read period, the compensation signal increasing the voltage at the first terminal whilst the output circuit generates the output signal, the compensation signal being a logically negated version of the transfer signal.