The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 13, 2010
Filed:
Jan. 24, 2008
Noriyuki Ito, Kawasaki, JP;
Noriyuki Ito, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
Shielded clock wiring used in an integrated circuit is designed by storing a table of identifiers of shielded clock wiring usable in the integrated circuit, storing dividing rule information in correspondence with each identifier, describing a way of dividing the shielded clock wiring indicated by the each identifier; inputting a wiring layer of a shielded clock wiring of a wiring request, inputting an identifier of the shielded clock wiring of the wiring request and inputting a starting point and an end point of the shielded clock wiring of the wiring request; specifying a dividing rule of the shielded clock wiring indicated by the identifier; and judging whether to permit the shielded clock wiring of the wiring request, by judging whether shielded clock wiring resulting from division based on the dividing rule is spatially permissible.