The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 13, 2010
Filed:
Dec. 19, 2006
Vito Dai, Santa Clara, CA (US);
Jie Yang, Sunnyvale, CA (US);
Norma Rodriguez, San Jose, CA (US);
Luigi Capodieci, San Cruz, CA (US);
Vito Dai, Santa Clara, CA (US);
Jie Yang, Sunnyvale, CA (US);
Norma Rodriguez, San Jose, CA (US);
Luigi Capodieci, San Cruz, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
Layout patterns are identified as problematic when they have particular parameters required to exceed standard limits. The problematic layout patterns are associated with preferred design rules in a DRC-Plus deck. Layout data is scanned to generate match locations of any problematic layout patterns. The match locations are forwarded to a DRC engine that compares layout parameters of the match locations to corresponding preferred layout rules in the DRC-Plus deck. The DRC-Plus check results are used to modify the layout to improve manufacturability of the layout.