The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2010

Filed:

Aug. 28, 2006
Applicants:

Yasushi Aoki, Kanagawa, JP;

Takanori Saeki, Kanagawa, JP;

Koichiro Kiguchi, Kanagawa, JP;

Inventors:

Yasushi Aoki, Kanagawa, JP;

Takanori Saeki, Kanagawa, JP;

Koichiro Kiguchi, Kanagawa, JP;

Assignee:

NEC Electronic Corporation, Kawasaki, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03D 3/24 (2006.01); H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a clock and data recover circuit including N flip-flops (F/Fs) for sampling an input data signal using N-phase clocks, a phase comparison circuit for performing phase comparison based on outputs of the F/Fs, a filter or smoothing a result of the phase comparison and outputting an up/down signal, up/down counters, each for receiving an output of the filter and counting up or down a count value thereof, a phase shift circuit for adjustably controlling phases of the clocks for edge detection and the clocks for data sampling according to phase control signals from an up/down counter and an up/down counter, respectively, and an up/down control circuit for receiving a control signal for controlling maximum and minimum values of count values of the up/down counter, generating a signal for controlling counting up and down of the up/down counter based on the count value of the up/down counter, and supplying the generated signal to the up/down counter.


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