Memory device with configurable delay tracking

Abstract

A memory device with configurable delay tracking is described. The memory device includes M normal word line drivers, a dummy word line driver a memory array, N sense amplifiers, and a timing control circuit. The memory array includes M rows and N columns of memory cells and a column of dummy cells. The word line drivers drive word lines for the rows of memory cells. The dummy word line driver drives a dummy word line for at least one dummy cell in the column of dummy cells. The timing control circuit generates enable signals having configurable delay, which may be obtained with an acceleration circuit that provides variable drive for a dummy bit line coupled to the column of memory cells. The sense amplifiers detect bit lines for the columns of memory cells based on the enable signals.