The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2010

Filed:

Mar. 12, 2008
Applicants:

Tomonori Terasawa, Tokyo, JP;

Nobukazu Murata, Tokyo, JP;

Inventors:

Tomonori Terasawa, Tokyo, JP;

Nobukazu Murata, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory cell array includes a plurality of memory cells disposed in matrix. A plurality of word lines extend in the row direction, and the gates in the memory cells disposed in each row are commonly connected to one of the word lines. A plurality of sub bit lines extend in the column direction, and the sources in the memory cells disposed in a first column and the drains in the memory cells disposed in a second column, which is adjacent to the first column, are commonly connected to one of the sub bit lines. A plurality of pairs of transistors are provided, each having a source selector and a drain selector. Each transistor pair is disposed at one of the locations at both ends of the sub bit lines, which are adjacent to each other, in a manner such that the transistor pairs sandwich the word lines from alternating sub bit ends.


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