The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2010

Filed:

Apr. 25, 2007
Applicant:

Atsushi Yagishita, Somers, NY (US);

Inventor:

Atsushi Yagishita, Somers, NY (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device that has a pMOS double-gate structure, has a substrate, the crystal orientation of the top surface of which is (100), a semiconductor layer that is made of silicon or germanium, formed on the substrate such that currents flow in a direction of a first <110> crystal orientation, and channels are located at sidewall of the semiconductor layer, a source layer that is formed on the substrate adjacent to one end of the semiconductor layer in the direction of first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a drain layer that is formed on the substrate adjacent to the other end of the semiconductor layer in the direction of first <110> crystal orientation and is made of a metal or metal silicide to form a Schottky junction with the semiconductor layer; a gate electrode that is formed on the semiconductor layer in a direction of a second <110> crystal orientation perpendicular to the current flow direction, and a gate insulating film that is disposed between the semiconductor layer and the gate electrode, wherein a uniaxial tensile strain is applied to the semiconductor layer in the direction of the second <110> crystal orientation perpendicular to the current flow direction.


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Yagishita, Atsushi. (2010). Finfet pmos double gate semiconductor device with uniaxial tensile strain applied to channel by shrinkable gate electrode material, current flow in <110> crystal orientation, and source and drain schottky contacts with channel and manufacturing method thereof (U.S. Patent No. 7755104). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7755104

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