The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7754549 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 13, 2010

Filed:

Aug. 16, 2007
Applicants:

Jae-beom Choi, Suwon-si, KR;

Young-jin Chang, Yongin-si, KR;

Yoon-seok Choi, Suwon-si, KR;

Seung-hwan Shim, Seongnam-si, KR;

Han-na JO, Cheongju-si, KR;

Jung-hoon Shin, Daejeon-si, KR;

Joon-young Koh, Gangreung-si, KR;

Inventors:

Jae-Beom Choi, Suwon-si, KR;

Young-jin Chang, Yongin-si, KR;

Yoon-Seok Choi, Suwon-si, KR;

Seung-Hwan Shim, Seongnam-si, KR;

Han-Na Jo, Cheongju-si, KR;

Jung-Hoon Shin, Daejeon-si, KR;

Joon-Young Koh, Gangreung-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a thin film transistor array panel includes forming an amorphous silicon film on an insulating substrate; forming a sacrificial film having an embossed surface on the amorphous silicon film; contacting a metal plate with the sacrificial film and performing heat-treatment for crystallizing the amorphous silicon film to change the amorphous silicon film to a polycrystalline silicon film; removing the metal plate and the sacrificial film; patterning the polycrystalline silicon film to form a semiconductor; forming a gate insulating layer which covers the semiconductor; forming a gate line on the gate insulating layer, a portion of the gate line overlapping the semiconductor; heavily doping a conductive impurity into portions of the semiconductor to form a source region and a drain region; forming an interlayer insulating layer which covers the gate line and the semiconductor; and forming a data line and an output electrode connected to the source and drain regions, respectively, on the interlayer insulating layer.


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