The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7752586 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 06, 2010

Filed:

Nov. 20, 2007
Applicant:

Toshihiko Yokota, Kyoto-fu, JP;

Inventor:

Toshihiko Yokota, Kyoto-fu, JP;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A design structure for an integrated circuit which includes: a first flip-flop which is capable of flushing and which operates by using a first clock signal CLK; a second flip-flop DFFwhich operates by using a second clock signal CLK, and which is connected to the first flip flop; and a third flip-flop DFFwhich operates by using the second clock signal CLK, and which is connected to the first flip-flop. A test on a path between the first and second flip-flops is carried out in a manner that test data is released and captured on receipt of the clock signal CLKbetween the second flip-flop DFFand the third flip-flop DFFvia the first flip-flop DFF, and that the test data is flushed by the first flip-flop DFF


Find Patent Forward Citations

Yokota, Toshihiko. (2010). Design structure of an integration circuit and test method of the integrated circuit (U.S. Patent No. 7752586). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7752586

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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