The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 2010
Filed:
Dec. 27, 2007
Hyun JO Yang, Cheongju-si, KR;
Hyun Jo Yang, Cheongju-si, KR;
Hynix Semiconductor Inc., Icheon-si, KR;
Abstract
Provided is a method for verifying a pattern of a semiconductor device. In the method, a designed layout of target patterns is provided, and transferring the designed layout on a wafer to form wafer patterns. Wafer patterns image contour is obtain. The image contour for wafer patterns on the designed layout are matched, After edge differences between the designed layout and the wafer patterns image contour are extracted, a checking layout for detecting wafer pattern defects is obtain by adding the edge differences on the designed layout. Defects on the checking layout is identified to verify the patterns in view of processes before fabrication of a photomask.