The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2010

Filed:

Jan. 18, 2008
Applicants:

Gil I. Winograd, Aliso Viejo, CA (US);

Morteza Cyrus Afghahi, Coto De Caza, CA (US);

Esin Terzioglu, Aliso Viejo, CA (US);

Inventors:

Gil I. Winograd, Aliso Viejo, CA (US);

Morteza Cyrus Afghahi, Coto De Caza, CA (US);

Esin Terzioglu, Aliso Viejo, CA (US);

Assignee:

Novelics, LLC, Aliso Viejo, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment, a read-only memory (ROM) is provided that includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cell transistors arranged in rows corresponding to the word lines such that if a word line is asserted the corresponding memory cell transistors are conducting, the memory cell transistors also being arranged in columns corresponding to the bit lines; wherein each column of memory cell transistors is arranged into column groups, each column group including an access transistor coupled to the corresponding bit line, the remaining transistors in the column group being coupled in series from the access transistor to a last transistor in the column group, the last transistor in the column group being coupled to a voltage node.


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