High speed cmos output buffer for nonvolatile memory devices

Abstract

An output CMOS buffer includes MOS enhancement transistors and has a second complementary pair of natural or low threshold transistors, connected respectively in parallel to transistors of opposite type of conductivity of the complementary pair of enhancement MOS transistors of the final buffer stage. The gate terminals of the pair of natural or low threshold transistors are controlled by respective inverters, each supplied through a slew rate limiter of the slope of the driving current and are respectively connected between the positive supply node of the output buffer and a negative (below ground potential) node and between the common ground node of the output buffer and a positive supply node. The negative voltage and the positive voltage on the nodes are at least equal to the absolute value of the threshold voltage of the natural or low threshold transistors.