The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2010

Filed:

Jun. 18, 2008
Applicants:

Sergey Shumarayev, Los Altos Hills, CA (US);

Wilson Wong, San Francisco, CA (US);

Tim Tri Hoang, San Jose, CA (US);

Thungoc M. Tran, San Jose, CA (US);

Richard G. Cliff, Los Altos, CA (US);

Inventors:

Sergey Shumarayev, Los Altos Hills, CA (US);

Wilson Wong, San Francisco, CA (US);

Tim Tri Hoang, San Jose, CA (US);

Thungoc M. Tran, San Jose, CA (US);

Richard G. Cliff, Los Altos, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
Abstract

High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit ('PLD') includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.


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