The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2010

Filed:

Aug. 04, 2008
Applicants:

Kenneth J. Goodnow, Essex Junction, VT (US);

Clarence R. Ogilvie, Huntington, VT (US);

Christopher B. Reynolds, Underhill, VT (US);

Jack R. Smith, S. Burlington, VT (US);

Sebastian T. Ventrone, S. Burlington, VT (US);

Inventors:

Kenneth J. Goodnow, Essex Junction, VT (US);

Clarence R. Ogilvie, Huntington, VT (US);

Christopher B. Reynolds, Underhill, VT (US);

Jack R. Smith, S. Burlington, VT (US);

Sebastian T. Ventrone, S. Burlington, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
Abstract

A reconfigurable logic array (RLA) having a logic capacity and configured to process a function having a total logic requirement that exceeds the logic capacity of the RLA. The RLA includes first and second storage regions and a plurality of programmable logic elements located between the first and second storage regions. When the function is parsed into a plurality of functional blocks, this configuration allows the RLA to process the function by sequentially processing the functional blocks in alternating directions within the RLA, using the plurality of programmable logic elements to sequentially process each of the functional blocks and using the first and second storage regions to temporarily hold the input and output for that one of the functional blocks.


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