The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7750511 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 06, 2010

Filed:

Apr. 10, 2007
Applicants:

Vikas Agarwal, Austin, TX (US);

Asit S. Ambekar, Austin, TX (US);

Sanjay Dubey, Austin, TX (US);

Saiful Islam, Austin, TX (US);

Inventors:

Vikas Agarwal, Austin, TX (US);

Asit S. Ambekar, Austin, TX (US);

Sanjay Dubey, Austin, TX (US);

Saiful Islam, Austin, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit (IC) includes power supply interconnects that couple to a power source. The integrated circuit includes electronic devices that perform desired functions and further includes decoupling capacitor circuits that provide noise reduction throughout the integrated circuit. In one embodiment, each decoupling capacitor circuit includes a decoupling capacitor and a switching circuit. The switching circuit connects the decoupling capacitor to the power supply interconnects during a connect mode when the switching circuit detects no substantial decoupling capacitor leakage. However, the switching circuit effectively disconnects the decoupling capacitor from the power supply interconnects during a disconnect mode when the switching circuit detects substantial decoupling capacitor leakage. The decoupling capacitor circuit self-initializes in the connect mode without external control signals and is thus self-contained. Because of the self-contained nature of the decoupling capacitor circuit, an integrated circuit may contain an array of decoupling capacitor circuits without expenditure of substantial chip real estate for respective decoupling capacitor control lines.


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