The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7750411 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 06, 2010

Filed:

Jun. 26, 2007
Applicants:

Hirofumi Harada, Chiba, JP;

Hisashi Hasegawa, Chiba, JP;

Hideo Yoshino, Chiba, JP;

Inventors:

Hirofumi Harada, Chiba, JP;

Hisashi Hasegawa, Chiba, JP;

Hideo Yoshino, Chiba, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a semiconductor integrated circuit device, which includes: a low-voltage MOS transistor having a source/drain region formed of a low impurity concentration region and a high impurity concentration region; and a high-voltage MOS transistor similarly having a source/drain region formed of a low impurity concentration region and a high impurity concentration region, in which, the source/drain high impurity concentration region of the low-voltage NMOS transistor is doped with arsenic, while the source/drain high impurity concentration region of the high-voltage NMOS transistor is doped with phosphorus.


Find Patent Forward Citations

Harada, Hirofumi. (2010). Semiconductor integrated circuit device (U.S. Patent No. 7750411). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7750411

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