The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 06, 2010
Filed:
Feb. 28, 2007
Kazuya Notsu, Chigasaki, JP;
Kiyofumi Sakaguchi, Yokohama, JP;
Nobuhiko Sato, Sagamihara, JP;
Hajime Ikeda, Chigasaki, JP;
Shoji Nishida, Hiratsuka, JP;
Kazuya Notsu, Chigasaki, JP;
Kiyofumi Sakaguchi, Yokohama, JP;
Nobuhiko Sato, Sagamihara, JP;
Hajime Ikeda, Chigasaki, JP;
Shoji Nishida, Hiratsuka, JP;
Canon Kabushiki Kaisha, Tokyo, JP;
Abstract
An SiGe layer is grown on a silicon substrate. The SiGe layer or the silicon substrate and SiGe layer are porosified by anodizing the SiGe layer to form a strain inducing porous layer or a porous silicon layer and strain inducing porous layer. An SiGe layer and strained silicon layer are formed on the resultant structure. The SiGe layer in the stacking growth step only needs to be on the uppermost surface of the porous layer. For this reason, an SiGe layer with a low defect density and high concentration can be formed. Since the SiGe layer on the strain inducing porous layer can achieve a low defect density without lattice mismatching. Hence, a high-quality semiconductor substrate having a high strained silicon layer can be obtained.