The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2010

Filed:

Apr. 25, 2003
Applicants:

Toshitsugu Sakamoto, Tokyo, JP;

Masakazu Aono, Saitama, JP;

Tsuyoshi Hasegawa, Saitama, JP;

Tomonobu Nakayama, Saitama, JP;

Hiroshi Sunamura, Tokyo, JP;

Hisao Kawaura, Tokyo, JP;

Naohiko Sugibayashi, Tokyo, JP;

Inventors:

Toshitsugu Sakamoto, Tokyo, JP;

Masakazu Aono, Saitama, JP;

Tsuyoshi Hasegawa, Saitama, JP;

Tomonobu Nakayama, Saitama, JP;

Hiroshi Sunamura, Tokyo, JP;

Hisao Kawaura, Tokyo, JP;

Naohiko Sugibayashi, Tokyo, JP;

Assignees:

Japan Science and Technology Agency, Kawaguchi-shi, JP;

Riken, Wako-shi, JP;

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 47/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a solid electrolyte switching device, which can maintain an on or off state when the power source is removed, the resistance of which in on the state is low, and which is capable of integration and re-programming, and FPGA and a memory device using the same, and a method of manufacturing the same. A solid electrolyte switching device (') comprises a substrate () in which surface is coated with an insulation layer, a first interconnection layer () set on said substrate (), an ion supplying layer () set on said first interconnection layer (), a solid electrolyte layer () set on said ion supplying layer (), an interlevel insulating layer () having a via hole set to cover said first interconnection layer (), said ion supplying layer (), and said solid electrolyte layer (), a counter electrode layer () set to contact said solid electrolyte layer () through the via hole of said interlevel insulating layer (), and a second interconnection layer () set to cover said counter electrode layer (). The switching device can be provided in which the on state, or the off state can be arbitrarily set by the threshold voltage applied between the ion supplying layer () and the counter electrode layer (), which is non-volatile, and the resistance of which in the on state is low. The switching device of the present invention is also simple and fine in structure, and hence makes it possible to provide smaller switching devices than are currently available. Further, using the switching device of the present invention as the switching device of an FPGA () makes it possible to provide re-programmable and fast operation FPGA (). Using the switching device of the present invention as a memory cell of a memory device makes it possible to provide a non-volatile memory device with high programming and reading speed.


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