The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2010

Filed:

Sep. 25, 2008
Applicant:

Seiichi Aritome, Yokohama, JP;

Inventor:

Seiichi Aritome, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8247 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing a nonvolatile semiconductor memory device including: forming a first and a second stacked gate structures, each of which including a first polysilicon layer formed on a silicon substrate via a gate insulator, an inter-gate insulator formed on the first polysilicon layer, a second polysilicon layer formed on the inter-gate insulator, and a cap layer formed on the second polysilicon layer, respectively; forming a interlayer insulator between the first and the second stacked gate structures, the interlayer insulator covering upper surfaces of the cap layer; planarizing the interlayer insulator by using the cap layers as a stopper; removing the cap layers so that the second polysilicon layers are exposed; masking the exposed second polysilicon layer of the first stacked gate structure by a photoresist film; removing the second polysilicon layer and the inter-gate insulator of the second stacked gate structure so that the first polysilicon layer of the second stacked gate structure is exposed; removing the photoresist film so that the second polysilicon of the first stacked gate structure is exposed; and forming conductive material layers, including a metal, on the exposed first polysilicon layer of the second stacked gate structure and the exposed second polysilicon layer of the first stacked gate structure.


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