The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 2010
Filed:
Feb. 25, 2008
David William Boerstler, Round Rock, TX (US);
Eskinder Hailu, Austin, TX (US);
Kazuhiko Miki, Round Rock, TX (US);
Jieming Qi, Austin, TX (US);
David William Boerstler, Round Rock, TX (US);
Eskinder Hailu, Austin, TX (US);
Kazuhiko Miki, Round Rock, TX (US);
Jieming Qi, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile