The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7747828 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 29, 2010

Filed:

Nov. 17, 2004
Applicants:

Yunsheng Wang, San Jose, CA (US);

Casey Springer, Portland, OR (US);

Tak Kwong Wong, Milpitas, CA (US);

Bill Beane, Gustine, CA (US);

Inventors:

Yunsheng Wang, San Jose, CA (US);

Casey Springer, Portland, OR (US);

Tak Kwong Wong, Milpitas, CA (US);

Bill Beane, Gustine, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A static random access memory (SRAM) includes an input read register (IRR) for monitoring the state of external binary devices and an output drive register (ODR) for controlling the state of external binary devices. The SRAM can be a multi-port device for access by multiple processors or controllers. Each bit of the IRR can mirror the state of a connected external binary device, and can be read to a connected processor using a standard read instruction. Each bit of the ODR can manipulate the state of a connected external binary device by providing the device with a path to the SRAM supply voltage. Each bit of the ODR can also be read without changing the state, or interrupting the operation of, the connected external binary device. When set to the proper mode, the addresses used for the IRR and ODR can be used with the SRAM main memory array for standard memory operations.


Find Patent Forward Citations

Loading…