The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7746712 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 29, 2010

Filed:

Apr. 04, 2008
Applicants:

Jae-sung Kang, Cheonan-si, KR;

Byung-heon Kwak, Suwon-si, KR;

Hyun-soon Jang, Seoul, KR;

Seung-whan Seo, Cheonan-si, KR;

Sang-joon Ryu, Asan-si, KR;

Hyun-tae Lim, Seoul, KR;

Inventors:

Jae-sung Kang, Cheonan-si, KR;

Byung-heon Kwak, Suwon-si, KR;

Hyun-soon Jang, Seoul, KR;

Seung-whan Seo, Cheonan-si, KR;

Sang-joon Ryu, Asan-si, KR;

Hyun-tae Lim, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a semiconductor memory device having a post package repair control circuit and a post package repair method. In the semiconductor memory device and the post package repair method, in a post package repair mode, a second memory bank is used as a fail bit map memory for storing failed bit information regarding a first memory bank, and the first memory bank is used as a fail bit map memory for storing failed bit information regarding the second memory bank.


Find Patent Forward Citations

Kang, Jae-sung. (2010). Semiconductor memory device including post package repair control circuit and post package repair method (U.S. Patent No. 7746712). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7746712

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