The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2010

Filed:

Mar. 07, 2008
Applicants:

Satoru Sekine, Anpachi-Gun, JP;

Yoshitaka Ueda, Ogaki, JP;

Takashi Asano, Anpachi-Gun, JP;

Shinji Furuichi, Maibara, JP;

Atsushi Wada, Ogaki, JP;

Inventors:

Satoru Sekine, Anpachi-Gun, JP;

Yoshitaka Ueda, Ogaki, JP;

Takashi Asano, Anpachi-Gun, JP;

Shinji Furuichi, Maibara, JP;

Atsushi Wada, Ogaki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A plurality of flip-flop circuits, having different circuit configurations, which perform an identical digital signal processing are mixed on a single semiconductor substrate. A first flip-flop circuit among the plurality of flip-flop circuits receives a clock signal supplied from outside the flip-flop circuits, through at least two stage inverters, and operates with clock signals outputted from the inverters. A second flip-flop circuit receives the clock signal supplied from outside the flip-flop circuits through at least one inverter having a less number of stages than the number of stages of the inverter contained in the first flip-flop circuit, and operates with at least one of the clock signal and a clock signal outputted from the inverter.


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