The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 2010
Filed:
Apr. 18, 2007
Sean Shau-tu LU, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Joseph Huang, Morgan Hill, CA (US);
Yan Chong, San Jose, CA (US);
Sean Shau-Tu Lu, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Joseph Huang, Morgan Hill, CA (US);
Yan Chong, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Digitally controlled delay-locked loops can have a phase detector, control logic, and a delay chain. The control logic generates digital signals in response to an output signal of the phase detector. The delay chain generates a delay that varies in response to the digital signals. In some embodiments, the control logic maintains logic states of the digital signals constant in response to an enable signal to maintain the delay of the delay chain constant in a lock mode of the digitally controlled delay-locked loop. In other embodiments, the delay of the delay chain varies by a discrete time period in response to a change in logic states of the digital signals, and the maximum phase error between a phase of the reference clock signal and a phase of the feedback clock signal is less than the discrete time period when the digitally controlled delay-locked loop is in a lock mode.