The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2010
Filed:
Mar. 22, 2007
Malay Ganai, Plainsboro, NJ (US);
Aarti Gupta, Princeton, NJ (US);
Malay Ganai, Plainsboro, NJ (US);
Aarti Gupta, Princeton, NJ (US);
NEC Laboratories America, Inc., Princeton, NJ (US);
Abstract
Verification friendly models for SAT-based formal verification are generated from a given high-level design wherein during construction the following guidelines are enforced: 1) No re-use of functional units and registers; 2) Minimize the use of muxes and sharing; 3) Reduce the number of control steps; 4) Avoid pipelines; 5) Chose functional units from 'verification friendly' library; 6) Re-use operations; 7) Perform property-preserving slicing; 8) Support 'assume' and “assert” in the language specification; and 8) Use external memory modules instead of register arrays.