The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2010
Filed:
Nov. 25, 2008
Applicants:
Takamoto Watanabe, Nagoya, JP;
Shigenori Yamauchi, Nisshin, JP;
Inventors:
Takamoto Watanabe, Nagoya, JP;
Shigenori Yamauchi, Nisshin, JP;
Assignee:
DENSO CORPORATION, Kariya, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/60 (2006.01);
U.S. Cl.
CPC ...
Abstract
An inverter circuit configuring a delay unit is a so-called CMOS transistor including a PMOS transistor and an NMOS transistor, of which respective gates are interconnected and respective drains are interconnected. The source and a back gate of the NMOS transistor are connected to the ground. The source of the PMOS transistor is connected to a positive drive terminal and controlled by an analog input signal. The back gate of the PMOS transistor is connected to a control terminal and controlled by a control signal.