The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2010

Filed:

Jan. 11, 2006
Applicants:

Yasushi Kubota, Sakurai, JP;

Kazuhiro Maeda, Kizugawa, JP;

Hajime Washio, Oxford, GB;

Patrick Zebedee, Oxford, GB;

Inventors:

Yasushi Kubota, Sakurai, JP;

Kazuhiro Maeda, Kizugawa, JP;

Hajime Washio, Oxford, GB;

Patrick Zebedee, Oxford, GB;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

A digital/analogue converter for converting an input n-bit digital code, where n is an integer greater than one, has an n-bit digital input and an output for connection to a load, and includes: an array of (n−1) switched capacitors; and a switching arrangement. In one example embodiment, the switching arrangement is adapted, in a zeroing phase of operation, to connect a first reference voltage to the first plate of at least one capacitor of the array and to connect a second plate of the at least one capacitor to a voltage that, for at least one value of the input digital code, is different from the first reference voltage and is further adapted, in a decoding phase of operation, to enable, dependent on the value of the input digital code, injection of charge into the at least one capacitor. In one example embodiment, the converter may be a bufferless converter having an output for direct connection to a capacitive load.


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