The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2010
Filed:
Apr. 11, 2007
Dharmaray M. Nedalgi, Bangalore, IN;
Dharmaray M. Nedalgi, Bangalore, IN;
NXP B.V., Eindhoven, NL;
Abstract
An electronic circuit is provided comprising an input (V) for coupling a circuit of a first voltage domain to the electronic circuit, and a first, second, third and fourth transistor coupled between a supply voltage (VDD) and a voltage (VSS). The third transistor (M) is coupled between the voltage (VSS) and a first node (tn). The second transistor (M) is coupled between a second node (tp) and the output (V). The third transistor (M) is coupled between the first node (tn) and the output (V). The fourth transistor (M) is coupled between the supply voltage (VDD) and the second node (tp). A first reference voltage generating unit (RC) receives the voltage at the first node (tn) and the voltage (VSS) as input, and its output is coupled to the gate of the second transistor (M). A second reference voltage generating unit (RD) receives the supply voltage (VDD) and the voltage of the second node (tp) as input, and its output is coupled to the gate of the third transistor (M). The first and second reference voltage generating units (RD, RC) generate a reference voltage according to at least one of the logic states of the first, second, third or fourth transistor (M-M).