The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2010
Filed:
Dec. 20, 2006
Xiangfeng Duan, Mountain View, CA (US);
Paul Bernatis, Sunnyvale, CA (US);
Alice Fischer-colbrie, Redwood City, CA (US);
James M. Hamilton, Sunnyvale, CA (US);
Francesco Lemmi, Sunnyvale, CA (US);
Yaoling Pan, Union City, CA (US);
J. Wallace Parce, Palo Alto, CA (US);
Cheri X. Y. Pereira, Fremont, CA (US);
David P. Stumbo, Belmont, CA (US);
Xiangfeng Duan, Mountain View, CA (US);
Paul Bernatis, Sunnyvale, CA (US);
Alice Fischer-Colbrie, Redwood City, CA (US);
James M. Hamilton, Sunnyvale, CA (US);
Francesco Lemmi, Sunnyvale, CA (US);
Yaoling Pan, Union City, CA (US);
J. Wallace Parce, Palo Alto, CA (US);
Cheri X. Y. Pereira, Fremont, CA (US);
David P. Stumbo, Belmont, CA (US);
Nanosys, Inc., Palo Alto, CA (US);
Abstract
The present invention is directed to methods to harvest, integrate and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides methods for harvesting nanowires that include selectively etching a sacrificial layer placed on a nanowire growth substrate to remove nanowires. The invention also provides methods for integrating nanowires into electronic devices that include placing an outer surface of a cylinder in contact with a fluid suspension of nanowires and rolling the nanowire coated cylinder to deposit nanowires onto a surface. Methods are also provided to deposit nanowires using an ink-jet printer or an aperture to align nanowires. Additional aspects of the invention provide methods for preventing gate shorts in nanowire based transistors. Additional methods for harvesting and integrating nanowires are provided.