The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2010
Filed:
Jan. 04, 2008
James R. Griffiths, Chandler, AZ (US);
James R. Griffiths, Chandler, AZ (US);
Freescale Semiconductor, Inc., Auustin, TX (US);
Abstract
A method () is described for an electronic assembly (). An electronic die () with a sacrificial layer () on its back () and electrical contacts () on its front () is temporarily attached by its front () to a substrate (). The back () is over-molded by a first material () extending over the substrate (). The substrate () is removed leaving the die contacts () and the first material () exposed. Interconnect layer(s) () are provided over the first material () and the die (), electrically coupled to the contacts (). Further components () can be coupled to the upper-most interconnects (). A second material () is over-molded over the components () and upper-most interconnects (). Thinning the first material () exposes the sacrificial layer () for removal. The die back () and vias () in the first material () extending to the first interconnect layer (-) laterally outside the die () are filled with a conductor (), providing single surface electrical and thermal contact (--), separated by just the die thickness from heat generating regions of the die ().