The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2010
Filed:
Jan. 23, 2006
Wibo Daniel Van Noort, Wappingers Falls, NY (US);
Franciscus Petrus Widdershoven, Eindhoven, NL;
Radu Surdeanu, Roosbeek, BE;
Wibo Daniel Van Noort, Wappingers Falls, NY (US);
Franciscus Petrus Widdershoven, Eindhoven, NL;
Radu Surdeanu, Roosbeek, BE;
NXP B.V., Eindhoven, NL;
Abstract
The invention provides a method of fabricating an extremely short-length dual-gate FET, using conventional semi-conductor processing techniques, with extremely small and reproducible fins with a pitch and a width that are both smaller than can be obtained with photolithographic techniques. On a protrusion () on a substrate (), a first layer () and a second layer () are formed, after which the top surface of the protrusion () is exposed. A portion of the first layer () is selectively removed relative to the protrusion () and the second layer (), thereby creating a fin () and a trench (). Also a method is presented to form a plurality of fins () and trenches (). The dual-gate FET is created by forming a gate electrode () in the trench(es) () and a source and drain region. Further a method is presented to fabricate an extremely short-length asymmetric dual-gate FET with two gate electrodes that can be biased separately.