The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2010
Filed:
Aug. 15, 2007
Po-hung Lin, Zhubei, TW;
Ho-che Yu, Kaohsiung, TW;
Tian-hau Tsai, Shulin, TW;
Shyh-chang Lin, Hsinchu, TW;
Shi-hong Bai, Hsinchu, TW;
Po-Hung Lin, Zhubei, TW;
Ho-Che Yu, Kaohsiung, TW;
Tian-Hau Tsai, Shulin, TW;
Shyh-Chang Lin, Hsinchu, TW;
Shi-Hong Bai, Hsinchu, TW;
Springsoft, Inc., Hsinchu, TW;
Abstract
A computer-based placement and routing (P&R) tool stores a set of circuit patterns, each describing a separate device group by referencing each device of the device group and by indicating which device elements forming the referenced devices are interconnected by nets, a set of placement patterns, each providing a guide for placing IC device elements forming a device group described by a corresponding one of the circuit patterns and a set of routing styles to act as guides for routing nets between device elements placed in particular patterns. To produce a layout for an analog IC described by a netlist, the P&R tool identifies each set of devices in the IC forming a device group described by any of the circuit patterns. The P&R tool then generates a separate device group layout for each identified device group using the placement patterns as guides for placing device elements within the device group layout and using the routing styles as guides for routing nets interconnecting device elements within the device group layout. The P&R tool also generates a layout for each device not included in any identified device group. The tool then generates a layout for the IC incorporating each generated device and device group layout.