The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7739627 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 15, 2010

Filed:

Jul. 02, 2007
Applicants:

Marko P. Chew, Palo Alto, CA (US);

Yue Yang, Cupertino, CA (US);

Inventors:

Marko P. Chew, Palo Alto, CA (US);

Yue Yang, Cupertino, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and a method of creating context dependent yield variants of integrated circuit ('IC') design components and using these variants during a physical design of an IC block to maximize manufacturing yield are described. A plurality of variants of each design component is generated and characterized with manufacturing yield as a function of neighboring context ('context') that includes, but is not limited to, neighboring design components and other layout objects and shapes. The present invention describes a system and method where a physical design process, in addition to satisfying design and performance requirements such as, but not limited to, power, timing, signal integrity and minimal layout area, selects context dependent yield variants to maximize manufacturing yield.


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Chew, Marko. (2010). System and method of maximizing integrated circuit manufacturing yield with context-dependent yield cells (U.S. Patent No. 7739627). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7739627

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