The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2010
Filed:
Apr. 20, 2007
Xuecheng Jin, Palo Alto, CA (US);
Andrey B Malinin, Fort Collins, CO (US);
John W. Kesterson, San Jose, CA (US);
Xuecheng Jin, Palo Alto, CA (US);
Andrey B Malinin, Fort Collins, CO (US);
John W. Kesterson, San Jose, CA (US);
iWatt Inc., Los Gatos, CA (US);
Abstract
A method and system of system-on-chip design that provides the benefits of reduced design time, a smaller die size, lower power consumption, and reduced costs in chip design and production. The process seeks to remove the worst performance and worst power case scenarios from the design and application phases. This is accomplished by planning the power supply voltage in the design phase along with its tolerance with process corner and temperature combinations. The established plan is then applied with communications between power supply integrated circuits and load system-on-chip.